1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit having a stack package structure and a method for measuring an internal voltage thereof.
2. Description of the Related Art
In general, packaging technology for semiconductor integrated circuits has been continuously developed to satisfy demands for miniaturization and mounting reliability thereof. As the high performance of electrical and electronic products is requested with the miniaturization of electrical and electronic products, a variety of technologies for a stack package of the semiconductor integrated circuits are being developed.
In the semiconductor industry, “stack” means vertically stacking two or more semiconductor chips or packages. A semiconductor memory device to which a stack package is applied may have a memory capacity two or more times larger than a memory capacity which may be realized in a semiconductor integration process. Furthermore, the stack package not only increases the memory capacity, but also increases mounting density and efficiency of the mounting area. Therefore, the research and development for the stack package are being accelerated.
The stack package may be fabricated by the following methods. First, individual semiconductor chips may be stacked, and then packaged at once. Second, packaged individual semiconductor chips may be stacked. The individual semiconductor chips of the stacked semiconductor package are electrically coupled through metallic wires or through-chip vias (TCVs). The stacked semiconductor package using TCVs has the physical and electrical connection between the semiconductor chips stacked vertically by TCVs formed in the respective semiconductor chips.
FIG. 1 is a diagram illustrating a semiconductor integrated circuit (hereinafter, referred to as ‘semiconductor memory’) including a plurality of semiconductor chips electrically connected through TCVs.
Referring to FIG. 1, the semiconductor memory 100 includes a first semiconductor chip 101 electrically connected to an external controller (not illustrated), second to fifth semiconductor chips 103, 105, 107, and 109 stacked vertically over the first semiconductor chip 101, and a plurality of first to fourth TCVs 111, 113, 115, and 117 formed by penetrating the second to fifth semiconductor chips 103, 105, 107, and 109, respectively.
The first semiconductor chip 101 is a semiconductor chip to control the second to fifth semiconductor chips 103, 105, 107, and 109 through the first to fourth TCVs 111, 113, 115, and 117 in response to various signals and voltages provided from the external controller, and it may be referred to as a master chip.
The second to fifth semiconductor chips 103, 105, 107, and 109 are semiconductor chips to perform given operations under the control of the first semiconductor chip 101, for example, store and provide data, and it may be referred to as slave chips.
The first to fourth TCVs 111, 113, 115, and 117 are formed of a metal having an excellent conductivity, and it may be referred to as through silicon vias (TSVs).
The semiconductor memory 100 configured in the above-described manner may interface semiconductor chips by transmitting various signals and voltages through the first to fourth TCVs 111, 113, 115, and 117, thereby reducing signal delay and current consumption. Furthermore, since the semiconductor memory 100 may have an improved bandwidth, the operation performance thereof is enhanced.
FIG. 2 illustrates a package structure in which the semiconductor memory 100 of FIG. 1 and the external controller are integrated.
Referring to FIG. 2, the external controller 200 such as a graphics processing unit (GPU) and the semiconductor memory 100 are electrically connected through a connection layer such as an interposer. Substantially, the first semiconductor chip 101 of the semiconductor memory 100 is electrically connected to the external controller 200 and controls the second to fifth semiconductor chips 103, 105, 107, and 109 through communication with the external controller 200.
Meanwhile, after the first to fifth semiconductor chips 101, 103, 105, 107, and 109 are individually fabricated, the semiconductor memory 100 may be completely fabricated through a subsequent packaging operation. In particular, in order to provide the semiconductor memory 100 having an excellent quality without defects, the quality state thereof is checked through a test during each process. In other words, after the first to fifth semiconductor chips 101, 103, 105, 107, and 109 are individually fabricated, the performances of the first to fifth semiconductor chips 101, 103, 105, 107, and 109 are checked through various tests, and the packaging operation is performed only on semiconductor chips which are determined to have no defects.
Here, the test may refer to a probe test. During the probe test, a probe of a test device are electrically connected with a pad provided in a test target chip and exposed to the outside, in order to test various performances of the test target chip.
Before stack packaging, that is, in a wafer state, pads provided in the first to fifth semiconductor chips 101, 103, 105, 107, and 109, respectively, are exposed to the outside. Therefore, a probe test may be performed on each of the first to fifth semiconductor chips 101, 103, 105, 107, and 109. However, after stack packaging, that is, in a package state, only the pad of the first semiconductor chip 101 positioned at the lowermost part is exposed to the outside. Therefore, a probe test may not be performed on each of the second to fifth semiconductor chips 103, 105, 107, and 109. For example, when the semiconductor memory 100 has a structure in which the second to fifth semiconductor chips 103, 105, 107, and 109 individually generate an internal voltage and the generated internal voltages are not shared among the first to fifth semiconductor chips 101, 103, 105, 107, and 109, the internal voltages generated by the second to fifth semiconductor chips 103, 105, 107, and 109, respectively, may not be tested after stack packaging.
FIG. 3 illustrates a semiconductor memory 100 including second to fifth semiconductor chips 103, 105, 107, and 109 each having an internal voltage generation circuit.
Referring to FIG. 3, the second to fifth semiconductor chips 103, 105, 107, and 109 include respective internal voltage generation circuits 103_1, 105_1, 107_1, and 109_1 for generating one or more internal voltages Vol_1 and Vol_2 and one or more pads PD_1 and PD_2 for testing the one or more internal voltages Vol_1 and Vol_2, respectively.
Here, the internal voltages Vol_1 and Vol_2 of the second to fifth semiconductor chips 103, 105, 107, and 109 may be measured through the pads PD_1 and PD_2 exposed to the outside in a wafer state. In a package state as illustrated in FIG. 3, however, since the pads PD_1 and PD_2 are not exposed to the outside, a test may not be performed on each of the second to fifth semiconductor chips 103, 105, 107, and 109.
In short, although the second to fifth semiconductor chips 103, 105, 107, and 109 pass a test in which the internal voltages Vol_1 and Vol_2 thereof are measured in a wafer state, the second to fifth semiconductor chips 103, 105, 107, and 109 may fail in a test in which the internal voltages Vol_1 and Vol_2 thereof are measured in a package state. This is because defects may occur during a stack packaging process due to characteristics of the stack packaging process. Therefore, the internal voltages Vol_1 and Vol_2 are to be retested in a package state. Accordingly, the semiconductor memory 100 is to be capable of testing the internal voltages Vol_1 and Vol_2 generated by the semiconductor chips 103, 105, 107, and 109 in a package stage.